Synchronous dynamic random-access memory (SDRAM) is a memory where the operation of its external in pin interface is coordinated by an externally supplied clock signal. Dynamic double data rate (DDR) SDRAM is a memory bus operating with DDR transfers of data on both the rising and falling edges of the clock signal. The Joint Electron Device Engineering Council (JEDEC) promulgates DDR SDRAM standards that are widely used in servers and personal computers today. For example, as of 2019, JEDEC has promulgated the DDR4 SDRAM standard.
For error correcting code (ECC) compatible memory, DDR4 defines a 72 bit parallel bidirectional single ended data bus. Each word transferred during a write or a read is 72 bits wide with 64 bits of data and 8 ECC bits, which is decoded by the memory controller into 64 bits of data. Typical memory modules include multiple ranks of 9 memory devices. A 72 bit transfer results in 8 bits read or written to each of the 9 devices. Burst reads are used to read an entire 64 byte cacheline of data through 8 sequential 8 byte reads.